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K4S561632E 4M x 16Bit x 4 Banks SDRAM

General Description

K4S561632E Features

K4S561632E Datasheet

K4S561632E Manufacturer

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General Description

The K4S561632E is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 16,777,216 words by 4 bits / 4 x 8,388,608 words by 8bits / 4 x 4,194,304 words by 16bits, fabricated with SAMSUNG's high performance CMOS technology.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.


Features

  • JEDEC standard 3.3V power supply
  • LVTTL compatible with multiplexed address
  • Four banks operation
  • MRS cycle with address key programs
    • CAS latency (2 & 3)
    • Burst length (1, 2, 4, 8 & Full page)
    • Burst type (Sequential & Interleave)
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst read single-bit write operation
  • DQM (x4,x8) & L(U)DQM (x16) for masking
  • Auto & self refresh
  • 64ms refresh period (8K Cycle)
  • 54pin TSOP II & 54pin sTSOP Pb, Pb-free Package (RoHS compliant)

 

Uses

  • BROADCAST/HDTV EQUIPMENT
  • TELECOMMUNICATIONS EQUIPMENT
  • HIGH-SPEED DATA ACQUISITION
  • CAD MONITORS/CCD IMAGE PROCESSING
  • NANO SECOND PULSE INTEGRATOR/PEAK DETECTORS
  • PULSE CODE MODULATOR/DEMODULATOR
  • COMPLETE VIDEO DC LEVEL RESTORATION
  • SAMPLE/HOLD AMPLIFIER

 

 

 
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